1. Field of the Invention
The present invention relates to a clock and data recovery circuit and related methods, and more specifically, the present invention discloses a clock and data recovery circuit and related methods capable of preventing transmitting signals from jittering.
2. Description of the Prior Art
In modern society, transmission and operation of a great deal of electronic data have improved human life, and information and knowledge with rapid exchanging speed have increased development of science and technology. In general, when transmitting or operating electronic data, a predetermined clock must be provided for accurately analyzing data contents of the electronic data and successfully processing operation of the electronic data.
To get corresponding clocks from input data for recovering data, a data recovery circuit is used. Please refer to FIG. 1. FIG. 1 is a block diagram of a data recovery circuit 10 according to the prior art. The data recovery circuit 10 can generate an output signal OUT that is synchronized with an input signal IN. The data recovery circuit 10 comprises a comparison circuit 18, a charge pump 20, a filter 24, a voltage control oscillator 26, and a 1/N frequency remover 27. The charge pump 20 comprises two bias circuits 22A and 22B, and two current sources Ip1 and Ip2. The bias circuits 22A and 22B are used to respectively supply working biases to allow the current sources Ip1 and Ip2 to operate normally. The current sources Ip1 and Ip2 are respectively controlled by two control signals CRA and CRB generated from the comparison circuit 18. After an addition effect, the current sources Ip1 and Ip2 generate a charge current Ip at a node P0 and transmit the charge current Ip to the filter 24. The filter 24 is a low-pass filter formed by a resistor Rp and two capacitors Cp and C0. After the charge current Ip generated from the charge pump 20 flows into the filter 24, the capacitor Cp will be charged and forms a control voltage Vp at a node P1. The oscillator 26 will be controlled by the control voltage Vp and generate an output signal OUT, which has a frequency corresponding to the control voltage Vp. That is, magnitude of the frequency of the output signal OUT generated from the oscillator 26 will be proportional to magnitude of the control voltage Vp (generally speaking, when the control voltage Vp is greater, the frequency of the control voltage Vp becomes higher). The output signal OUT will be transmitted to the frequency remover 27 to remove the frequency of the output signal OUT, and then feedback to the comparison circuit 18. Finally, the comparison circuit 18 will compare a phase difference between the input signal IN and the output signal OUT, and control the current sources Ip1 and Ip2 of the charge pump 20 according to the phase difference.
After being controlled by the comparison circuit 18, the charge pump 20 generates the corresponding charge current Ip, and the charge current Ip will correspondingly change the control voltage Vp of the filter 24 and further control the oscillator 26 to adjust the frequency and phase of the output signal OUT so as to allow the output signal OUT to be synchronized with the input signal IN. Finally, the output signal OUT has the same phase as the input signal IN through the adjustment of the frequency and phase of the output signal OUT by the data recovery circuit 10.
Please refer to FIG. 2. FIG. 2 shows oscillograms of related signals of the data recovery circuit 10 when the data recovery circuit 10 operates according to the prior art. As shown in FIG. 2, a horizontal axis indicates time, and a vertical axis of each waveform indicates magnitude of amplitude. For example, the control signal CRA is at a high level during a time interval dt1, and the control signal CRB is at a high level during a time level dt2+dt3. To enable the oscillator 26 to adjust the output signal OUT so as to compensate the above periodic errors, the control voltage Vp must be changed corresponding to the periodic errors. That is, the control voltage Vp is changeable for reacting to the phase difference between the input signal IN and the output signal OUT so as to allow the oscillator 26 to adjust the frequency and phase of the output signal OUT according to a changing situation of the control voltage Vp.
To achieve the aforementioned objective, operation of the data recovery circuit 10 can be illustrated as follows. When the data recovery circuit 10 operates, the control signals CRB and CRA are used to control current of the current sources Ip1 and Ip2. That is, when the control signal CRB or CRA is high, the corresponding current source Ip1 or Ip2 is switched on and supplies a certain current I; when the control signal CRB or CRA is low, the corresponding current source Ip1 or Ip2 is switched off and does not supply current. Therefore, during a time interval between tp0 and tp1, magnitude of the charge current Ip supplied by the current source Ip1 is I such that the charge current Ip will cause the control voltage Vp of the filter 24 to increase from a voltage Vp0 to a voltage Vp1. Since the time interval between tp0 and tp1 is dt1, an increasing range of the control voltage Vp will be proportional to the time interval dt1. During a time interval between tp2 and tp3, the control signal CRB causes the current source Ip2 to control the charge current Ip so as to allow the charge current Ip to discharge to the capacitors C0 and Cp, and to decrease magnitude of the control voltage Vp from Vp1 to Vp2. In general, during a time interval between tp0 and tp3, the control voltage Vp firstly increases from Vp0 to Vp1, and then decreases from Vp1 to Vp2. Therefore, a difference between the Vp0 and Vp2 of the control voltage Vp will respond to a phase difference between the input signal IN and the output signal OUT. Furthermore, the oscillator 26 can adjust the frequency and phase of the output signal OUT according to change of the control voltage Vp.
A defect of operating manner of the data recovery circuit 10 is to cause the phase difference of the control voltage Vp to have a large jitter. As mentioned above, the control voltage Vp is used to show the phase difference between the input signal IN and the output signal OUT. Since the voltage change between the voltage Vp0 and the voltage Vp2 responds to the phase difference, the way to show the phase difference is simply to change the control voltage Vp from the voltage Vp0 to the voltage Vp2. In the data recovery circuit 10, the control voltage Vp first increases from Vp0 to Vp1, and then decreases from Vp1 to Vp2. Therefore, this will cause the output signal OUT to jitter.
Please refer to FIG. 3. FIG. 3 shows an oscillogram of the output signal OUT generated from the prior data recovery circuit 10 when the output signal OUT is jittered. As shown in FIG. 3, a horizontal axis indicates time, and a vertical axis indicates magnitude of waveform. Since the oscillator 26 is controlled by the control voltage Vp, variance of the control voltage Vp will influence the output signal OUT generated from the oscillator 26. Transient states of the variance of the control voltage Vp will cause the frequency of the output signal OUT to float so that the output signal OUT will have periods with irregular variance. When the period of the output signal OUT is changed from tp0 to tp3, that is, the voltage of the control voltage Vp is changed from Vp0 to Vp2, the frequency of the output signal OUT will turn high or low due to the transient variance of the control voltage Vp. This is called the signal jitter. The signal jitter with frequency of irregular variance will be accumulated and interfere with the period of the output signal OUT so that the output signal OUT cannot be correctly synchronized with the input signal IN. Since the signal jitter generated from the output signal OUT is a high-frequency signal jitter, the high-frequency signal jitter is difficult to compensate through a feedback method of the data recovery circuit 10 itself. The filter 24 of the data recovery circuit 10 has a low-pass characteristic to filter out period errors of the high-frequency signal jitter caused between the input signal IN and the output signal OUT. This situation will cause the data recovery circuit 10 to have hardly compensating the high-frequency signal jitter, and cause the output signal OUT to spend more time synchronizing with the input signal IN.